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Features
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Master and Slave Operation Possible Supply Voltage up to 40V Operating voltage VS = 5V to 27V Typically 10 A Supply Current During Sleep Mode Typically 40 A Supply Current in Silent Mode Linear Low-drop Voltage Regulator: - Normal, Fail-safe, and Silent Mode * ATA6628 VCC = 3.3V 2% * ATA6630 VCC = 5.0V 2% - In Sleep Mode VCC is Switched Off VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical Combined at Open Drain Output NRES High-speed Mode Up to 115 kBaud Internal 1:6 Voltage Divider for VBattery Sensing Negative Trigger Input for Watchdog Boosting the Voltage Regulator Possible with an External NPN Transistor LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2 Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up Resistor Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery Adjustable Watchdog Time via External Resistor Advanced EMC and ESD Performance Fulfills the OEM "Hardware Requirements for LIN in Automotive Applications Rev.1.1" Interference and Damage Protection According ISO7637 Package: QFN 5 mm x 5 mm with 20 Pins
* * * * * * * * * * * * * *
LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog ATA6628 ATA6630 Preliminary
1. Description
The ATA6628 is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator for 3.3V/50 mA output and a window watchdog. The ATA6630 has the same functionality as the ATA6628; however, it uses a 5V/50 mA regulator. The voltage regulator is able to source 50 mA, but the output current can be boosted by using an external NPN transistor. This chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for LIN-bus systems. ATA6628/ATA6630 are designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data communication up to 20 kBaud. Sleep Mode and Silent Mode guarantee very low current consumption.
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Figure 1-1.
Block Diagram
20 VS Normal and Fail-safe Mode
11 INH 7 RXD
PVCC 5k
Receiver
Normal and Fail-safe Mode 6 RF Filter LIN
4 WAKE 17 KL_15 PVCC 12 TXD Edge Detection Wake-up Bus Timer
TXD Time-out Timer
Slew Rate Control
Short Circuit and Overtemperature Protection
Control Unit 2 EN
Debounce Time
Mode Select
Normal/Silent/ Fail-safe Mode 3.3V/50 mA/2% 5V/50 mA/2% Undervoltage Reset
19 18 13 NRES VCC PVCC
10 SP_MODE
High Speed Mode Watchdog Adjustable Watchdog Oscillator 14 WD_OSC
8 DIV_ON PVCC Internal Testing Unit 1 VBATT 9 PV 5 GND 3 NTRIG 16 MODE 15 TM
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2. Pin Configuration
Figure 2-1. Pinning QFN20
MODE 16 15 TM WD_OSC NRES TXD INH 14 QFN 5 mm 5 mm 0.65 mm pitch 20 lead 13 12 11 6 LIN 7 RXD 8 DIV_ON 9 PV 10 SP_MODE PVCC 18 KL15 17 VCC 19 VS 20 VBATT EN NTRIG WAKE GND 1 2 3 4 5
ATA6628/30
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Backside
Pin Description
Symbol VBATT EN NTRIG WAKE GND LIN RXD DIV_ON PV SP_MODE INH TXD NRES WD_OSC TM MODE KL_15 PVCC VCC VS Function Battery supply for the voltage divider Enables the device into Normal Mode Low-level watchdog trigger input from microcontroller; if not needed, connect to PVCC High-voltage input for local wake-up request; if not needed, connect to VS System ground LIN-bus line input/output Receive data output Input to switch on the internal voltage divider, active high Voltage divider output Input to switch the transceiver in High-speed Mode, active high Battery related High-side switch Transmit data input; active low output (strong pull down) after a local wake up request Output undervoltage and watchdog reset (open drain) External resistor for adjustable watchdog timing; if not needed, connect to GND For factory testing only (tie to ground) Low watchdog is on; high watchdog is off Ignition detection (edge sensitive) 3.3V/5V regulator sense input pin, connect to VCC 3.3V/5V regulator output/driver pin, connect to PVCC Battery supply Heat slug is connected to GND
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3. Functional Description
3.1 Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions.
3.2
Supply Pin (VS)
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS falls below VSth in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e., 3.3V/5V/50 mA output capability). The supply current is typically 10 A in Sleep Mode and 40 A in Silent Mode.
3.3
Ground Pin (GND)
The ATA6628/ATA6630 does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. The mandatory system ground is pin 5.
3.4
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads up to 50 mA. It is able to supply the microcontroller and other ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used, with its base connected to the VCC pin and its emitter connected to PVCC.
3.5
Voltage Regulator Sense Pin (PVCC)
The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e., when only using the internal output transistor), this pin must be connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e., its emitter terminal.
3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN 2.x specification are implemented. The allowed voltage range is between -27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled.
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3.7 Input/Output Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output and is signalling the fail-safe source. It is current-limited to < 8 mA.
3.8
TXD Dominant Time-out Function
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low for longer than tDOM > 27 ms, the LIN-bus driver is switched to recessive state. Nevertheless, when switching to Sleep Mode, the actual level at the TXD pin is relevant. To reactivate the LIN bus driver, switch TXD to high (> 10 s).
3.9
Output Pin (RXD)
This output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5 k to PVCC. The AC characteristics can be defined with an external load capacitor of 20 pF. The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V). During Fail-safe Mode it is signalling the fail-safe source.
3.10
Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/50 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and the current consumption is reduced to IVS typ. 40 A. The VCC regulator has its full functionality. If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage regulator is switched off.
3.11
Wake Input Pin (WAKE)
The WAKE Input pin is a high-voltage input used to wake up the device from Sleep Mode or Silent Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10 A, is implemented. If a local wake-up is not needed in the application, connect the WAKE pin directly to the VS pin.
3.12
Mode Input Pin (MODE)
Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of the connected microcontroller, connect MODE pin to PVCC and the watchdog is switched off.
Note: If you do not use the watchdog, connect pin MODE directly to PVCC.
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3.13
TM Input Pin
The TM pin is used for final production measurements at Atmel(R). In normal application, it has to be always connected to GND.
3.14
KL_15 Pin
The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge-sensitive pin (low-to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on. Although KL_15 pin is at high voltage (VBatt), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical Tdb Kl_15 of 160 s is implemented. The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin against voltage transients, a serial resistor of 47 k and a ceramic capacitor of 100 nF are recommended. With this RC combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition KL_15. You can also increase the wake-up time using external capacitors with higher values.
3.15
INH Output Pin
The INH Output pin is used to switch an external voltage regulator on during Normal and Fail-safe Mode. The INH Output is a high-side switch, which is switched-off in Sleep and Silent Mode. It is possible to switch off the external 1 k master resistor via the INH pin for master node applications.
3.16
Reset Output Pin (NRES)
The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a watchdog failure.
3.17
WD_OSC Output Pin
The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34 k and 120 k to adjust the watchdog oscillator time. If the watchdog is disabled, this voltage is switched off and you can either tie to GND or leave this pin open.
3.18
NTRIG Input Pin
The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger.
3.19
Wake-up Events from Sleep or Silent Mode
* LIN-bus * WAKE pin * EN pin * KL_15
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3.20 DIV_ON Input Pin
The DIV_ON pin is a low voltage input. It is used to switch on or off the internal voltage divider PV output directly with no time limitation (see Table 3-1 on page 7). It is switched on if DIV_ON is high or it is switched off if DIV_ON is low. In Sleep Mode the DIV_ON functionality is disabled and PV is off. An internal pull-down resistor is implemented.
3.21
VBATT Input Pin
The VBATT is a high voltage input pin to supply the internal voltage divider. In an application with battery voltage monitoring, this pin is connected to VBattery via a 47 resistor in series and a 10 nF capacitor to GND (see Figure 9-2 on page 31). The the divider ratio is 1:6.
3.22
PV Output Pin
For applications with battery monitoring, this pin is directly connected to the ADC of a microcontroller. For buffering the ADC input an external capacitor might be needed. This pin guarantees a voltage and temperature stable output of a VBattery ratio. The PV output pin is controlled by the DIV_ON input pin.
Table 3-1.
Table of Voltage Divider
Mode of Operation Fail-safe/Normal/ High-speed/Silent Sleep Input DiV_ON 0 1 0 1 Voltage Divider Output PV Off On Off Off
3.23
SP_MODE Input Pin
The SP_MODE pin is a low-voltage input. High-speed Mode of the transceiver can be activated via a high level during Normal Mode. Return to LIN 2.x Transceiver Mode with slope control is possible if you switch the SP_MODE pin to low.
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4. Modes of Operation
Figure 4-1. Modes of Operation
Unpowered Mode (See Section 4.5) a: VS > VSthF b: VS < VSthU c: Bus wake-up event d: Wake up from WAKE or KL_15 pin e: NRES switches to low b b c+d+e
b
a
Fail-safe Mode b e EN = 1
Go to silent command
VCC: 3.3V/5V/50 mA with undervoltage monitoring Communication: OFF Watchdog: ON EN = 1 c+d
Normal Mode VCC: 3.3V/5V/50 mA with undervoltage detection watchdog: ON High level at pin SP_MODE: High-speed Mode Transceiver 115 kBaud LIN 2.1 Transceiver 20 kBaud TXD time-out timer on
EN = 0 TXD = 1
Go to normal command
Silent Mode VCC: 3.3V/5V/50 mA with undervoltage monitoring Communication: OFF Watchdog: OFF
EN = 1
Go to sleep command
Sleep Mode VCC: switched off Communication: OFF Watchdog: OFF
EN = 0 TXD = 0
Table 4-1.
Mode of Operation Unpowered Fail-safe Normal/ High-speed Silent Sleep
Table of Modes
Transceiver Off Off On Off Off Pin LIN Recessive Recessive TXD depending Recessive Recessive VCC On 3.3V/5V 3.3V/5V 3.3V/5V 0V Pin Mode GND GND GND GND GND Watchdog On On On Off Off Pin WD_OSC On 1.23V 1.23V 0V 0V Pin INH Off On On Off Off
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4.1 Normal Mode
This is the normal transmitting and receiving mode. The voltage regulator is active and can source up to 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode.
4.2
Silent Mode
A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode Select window (see Figure 4-2 on page 9). The transmission path is disabled in Silent Mode. The INH output is switched off and the voltage divider is enabled. The overall supply current from VBatt is a combination of the IVSsi = 40 A plus the VCC regulator output current IVCC. The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. The internal slave termination between the LIN pin and the VS pin is disabled in Silent Mode to minimize the current consumption in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 A) between the LIN pin and the VS pin is present. Silent Mode can be activated independently from the actual level on the LIN, WAKE, or KL_15 pins. If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to Fail-safe Mode. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. Figure 4-2. Switch to Silent Mode
Normal Mode Silent Mode
EN
TXD
Mode select window td = 3.2 s
NRES
VCC
Delay time silent mode td_silent = maximum 20 s LIN LIN switches directly to recessive mode
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A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and the following rising edge at the LIN pin (see Figure 4-3 on page 10) result in a remote wake-up request which is only possible if TXD is high. The device switches from Silent Mode to Fail-safe Mode. The internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 4-3 on page 10). EN high can be used to switch directly to Normal Mode. Figure 4-3. LIN Wake-up from Silent Mode
Bus wake-up filtering time tbus Fail-safe mode Normal mode
LIN bus
Don't care
Node in silent mode
RXD
High
Low
High
TXD
Watchdog
Watchdog off
Start watchdog lead time td
VCC voltage regulator
Silent mode 3.3V/5V/50 mA
Fail safe mode 3.3V/5V/50 mA
Normal mode
EN High EN
NRES
Undervoltage detection active
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4.3 Sleep Mode
A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-4 on page 11). In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2 s earlier to Low than the TXD. Therefore, the best an easiest way are two falling edges at TXD and EN at the same time. The transmission path is disabled in Sleep Mode. The supply current IVSsleep from VBatt is typically 10 A. The INH output, the PV output and the VCC regulator are switched off. NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is disabled to minimize the current consumption in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 A) between the LIN pin and the VS pin is present. Sleep Mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. Figure 4-4. Switch to Sleep Mode
Sleep Mode EN
Normal Mode
Mode select window TXD td = 3.2 s NRES
VCC
Delay time sleep mode td_sleep = maximum 20 s LIN LIN switches directly to recessive mode
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A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t bus ) and a rising edge at pin LIN result in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode. The VCC regulator is activated, and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 4-5 on page 12). EN high can be used to switch directly from Sleep/Silent to Fail-safe Mode. If EN is still high after VCC ramp up and undervoltage reset time, the IC switches to the Normal Mode. Figure 4-5. LIN Wake Up from Sleep Mode
Bus wake-up filtering time tbus Fail-safe Mode Normal Mode
LIN bus
RXD
Low or floating
Low
TXD
VCC voltage regulator
On state Off state
Regulator wake-up time EN EN High
Reset time NRES Floating Microcontroller start-up time delay Watchdog Watchdog off Start watchdog lead time td
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4.4 Sleep or Silent Mode: Behavior at a Floating LIN-bus or a Short Circuited LIN to GND
In Sleep or in Silent Mode the device has a very low current consumption even during short-circuits or floating conditions on the bus. A floating bus can arise if the Master pull-up resistor is missing, e.g., if it is switched off when the LIN- Master is in sleep mode or even if the power supply of the Master node is switched off. In order to minimize the current consumption IVS in sleep or silent mode during voltage levels at the LIN-pin below the LIN pre-wake threshold, the receiver is activated only for a specific time tmon. If tmon elapses while the voltage at the bus is lower than Pre-wake detection low (VLINL) and higher than the LIN dominant level, the receiver is switched off again and the circuit changes back to sleep respectively Silent Mode. The current consumption is then the result of IVSsleep or IVSsilent plus ILINwake. If a dominant state is reached on the bus no wake-up will occur. Even if the voltage rises above the Pre-wake detection high (VLINH), the IC will stay in sleep respectively silent mode (see Figure 4-6). This means the LIN-bus must be above the Pre-wake detection threshold VLINH for a few microseconds before a new LIN wake-up is possible. Figure 4-6. Floating LIN-bus During Sleep or Silent Mode
LIN Pre-wake VLINL LIN BUS LIN dominant state VBUSdom
tmon IVSfail IVSsleep + ILINwake IVSsleep
IVS
IVSsleep/silent
Mode of operation Int. Pull-up Resistor RLIN
Sleep/Silent Mode
Wake-up Detection Phase
Sleep/Silent Mode
off (disabled)
If the ATA6628/ATA6630 is in Sleep or Silent Mode and the voltage level at the LIN-bus is in dominant state (VLIN < VBUSdom) for a time period exceeding tmon (during a short circuit at LIN, for example), the IC switches back to Sleep Mode respectively Silent Mode. The V S current consumption then consists of IVSsleep or IVSsilent plus ILINWAKE. After a positive edge at pin LIN the IC switches directly to Fail-safe Mode (see Figure 4-7 on page 14).
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Figure 4-7.
Short Circuit to GND on the LIN bus During Sleep- or Silent Mode
LIN Pre-wake LIN BUS VLINL LIN dominant state VBUSdom
tmon tmon
IVSfail
IVS
IVSsleep/silent
IVSsleep/silent + ILINwake
Mode of operation Int. Pull-up Resistor RLIN
Sleep/Silent Mode
Wake-up Detection Phase
Sleep/Silent Mode
Fail-Safe Mode
off (disabled)
on (enabled)
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4.5 Fail-safe Mode
The device automatically switches to Fail-safe Mode at system power-up. The voltage regulator is switched on (VCC = 3.3V/5V/2%/50 mA) (see Figure 5-1 on page 19). The NRES output switches to low for tres = 4 ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power down of VBatt (VS < VSthU) during Silent or Sleep Mode switches the IC into Fail-safe Mode after power up. A low at NRES switches into Fail-safe Mode directly. During Fail-safe Mode, the TXD pin is an output and signals the fail-safe source. The watchdog is switched on. The LIN SBC can operate in different Modes, like Normal, Silent, or Sleep Mode. The functionality of these modes is described in Table 4-2.
Table 4-2.
Fail-safe Mode Normal Mode Silent Mode
TXD, RXD Depending from Operation Modes
TXD Follows data transmission High High RXD Signalling fail-safe sources (see Table 4-3 and Table 4-4)
Different Modes
A wake-up event from either Silent or Sleep Mode will be signalled to the microcontroller using the two pins RXD and TXD. The coding is shown in Table 4-3. A wake-up event will lead the IC to the Fail-safe Mode.
Table 4-3.
Signalling Fail-safe Sources
TXD Low Low High RXD Low High Low
Fail-safe Sources LIN wake-up (pin LIN) Local wake-up (at pin Wake, pin KL15) VSth (battery) undervoltage detection
Table 4-4.
Signalling in Fail-safe Mode after Reset (NRES was Low), Shows the Reset Source at TXD and RXD Pins
TXD High High RXD Low High
Fail-safe Sources VCC undervoltage at NRES Watchdog reset at NRES
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4.6
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 5-1 on page 19). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset . During this time, treset, no mode change is possible. IF VS drops below VSth, then the IC switches to Unpowered Mode. The behavior of VCC, NRES and LIN is shown in Figure 4-8. The watchdog needs to be triggered. Figure 4-8. VCC versus VS for the VCC = 3.3V Regulator
6 .0 5.5 5.0 4 .5 Regulator drop voltage VD LIN
V in V
4 .0 3 .5 3 .0 2 .5 2 .0 1.5 1.0 0 .5 0 .0 0 .0 0 .5 1.0 1.5 2 .0 2 .5 3 .0 3 .5 4 .0 4 .5 5.0 VCC VS NRES
5.5
6 .0
VS in V
4.7
High-speed Mode
If SP_MODE pin is high and the IC is in Normal Mode, the slew rate control is switched off. The slope time of the LIN falling edge is tS_Fall < 2 s. The slope time of the LIN rising edge strongly depends on the LIN capacitive and resistive load. To achieve a high baud rate it is recommended to use a small resistor (500) and a low capacitor. This allows very fast data transmission up to 115 kBaud, e.g., for electronic control (ECU) tests and microcontroller program or data download. In this mode superior EMC performance is not guaranteed.
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5. Wake-up Scenarios from Silent or Sleep Mode
5.1 Remote Wake-up via Dominant Bus State
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (tBUS) and a rising edge at pin LIN result in a remote wake-up request. A remote wake-up from Silent Mode is only possible if TXD is high. The device switches from Silent or Sleep Mode to Fail-safe Mode. The VCC voltage regulator is/remains activated, the INH pin is switched to high, and the internal slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller and a strong pull down at TXD.
5.2
Local Wake-up via Pin WAKE
A falling edge at the WAKE pin followed by a low level maintained for a certain time period (tWAKE) results in a local wake-up request. The device switches to Fail-safe Mode. The internal slave termination resistor is switched on. The local wake-up request is indicated by a low level at the TXD pin to generate an interrupt for the microcontroller. When the Wake pin is low, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to high > 10 s before the negative edge at WAKE starts a new local wake-up request.
5.3
Local Wake-up via Pin KL_15
A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15) results in a local wake-up request. The device switches into the Fail-safe Mode. The internal slave termination resistor is switched on. The extra long wake-up time ensures that no transients at KL_15 create a wake-up. The local wake-up request is indicated by a low level at the TXD pin to generate an interrupt for the microcontroller. During high-level voltage at pin KL_15, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to low > 250 s before the positive edge at KL_15 starts a new local wake-up request. With external RC combination, the time is even longer.
5.4
Wake-up Source Recognition
The device can distinguish between different wake-up sources (see Table 4-4 on page 15). The wake-up source can be read on the TXD and RXD pin in Fail-safe Mode. These flags are immediately reset if the microcontroller sets the EN pin to high (see Figure 4-3 on page 10 and Figure 4-5 on page 12) and the IC is in Normal mode.
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5.5
Fail-safe Features
* During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator works independently. * During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode and even in this case the current consumption is lower than 45 A in Sleep Mode and lower than 80 A in Silent Mode. If the short-circuit disappears, the IC starts with a remote wake-up. * Sleep or Silent Mode: During a floating condition on the bus the IC switches back to Sleep Mode/Silent Mode automatically and thereby the current consumption is lower than 45 A/80 A. * The reverse current is < 2 A at the LIN pin during loss of VBatt. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. * During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller if NRES is connected to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of the Fail-safe Mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can start with its normal operation. * EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. * RXD pin is set floating if VBatt is disconnected. * TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. * If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE * If the WD_OSC pin has a short-circuit to GND and the NTRIG Signal has a period time > 27 ms a reset is guaranteed. * If the resistor at the WD_OSC pin is disconnected and the NTRIG Signal has a period time < 46 ms a reset is guaranteed. * If there is no NTRIG signal and a short-circuit at WD_OSC to GND the NRES switches to low after 90 ms. For an open circuit (no resistor) at WD_OSC it switches to low after 390 ms.
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5.6 Voltage Regulator
The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8 F and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current IVCC , which is needed for the application. In Figure 5-2 on page 19 the safe operating area of the ATA6628/ATA6630 is shown. Figure 5-1. VCC Voltage Regulator: Ramp-up and Undervoltage Detection
VS 12V
5.5V/3.8V
t
VCC 5V/3.3V Vthun
TVCC NRES 5V/3.3V
TReset
Tres_f
t
t
Figure 5-2.
Power Dissipation: Safe Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures Due to Rthja = 35 K/W
60 Tamb = 105C Tamb = 125C 40 50
IVCC/mA
30 20
10
0 3 5 7 9 11 13 15 17 19
VS/V
For microcontroller programming, it may be necessary to supply the VCC output via an external power supply while the VS Pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip. 19
9117E-AUTO-07/10
6. Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of T w d . The trigger signal must exceed a minimum time ttrigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34 k to 120 k). During Silent or Sleep Mode the watchdog is switched off to reduce current consumption. The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as lead time td. After wake up from Sleep or Silent Mode, the lead time td starts with the negative edge of the RXD output.
6.1
Typical Timing Sequence with RWD_OSC = 51 k
The trigger signal T wd is adjustable between 20 ms and 64 ms using the external resistor RWD_OSC. For example, with an external resistor of RWD_OSC = 51 k 1%, the typical parameters of the watchdog are as follows: tosc = 0.405 x RWD_OSC - 0.0004 x (RWD_OSC)2 (RWD_OSC in k ; tosc in s) tOSC = 19.6 s due to 51 k td = 7895 x 19.6 s = 155 ms t1 = 1053 x 19.6 s = 20.6 ms t2 = 1105 x 19.6 s = 21.6 ms tnres = constant = 4 ms After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset (typically 4 ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead time, t d , follows the reset and is td = 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a watchdog reset with tNRES = 4 ms will reset the microcontroller after td = 155 ms. The times t1 and t2 have a fixed relationship. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6 ms. To avoid false triggering from glitches, the trigger pulse must be longer than tTRIG,min > 200 ns. This slope serves to restart the watchdog sequence. If the triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed window t1 immediately switches NRES to low.
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Figure 6-1. Timing Sequence with RWD_OSC = 51 k
VCC 3.3V/5V Undervoltage Reset NRES treset = 4 ms Watchdog Reset tnres = 4 ms
td = 155 ms t1 = 20.6 ms twd t2 = 21 ms
t1
t2
NTRIG
ttrig > 200 ns
6.2
Worst Case Calculation with RWD_OSC = 51 k
The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst case calculation for the watchdog period twd is calculated as follows. The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2. t1,min = 0.8 x t1 = 16.5 ms, t1,max = 1.2 x t1 = 24.8 ms t2,min = 0.8 x t2 = 17.3 ms, t2,max = 1.2 x t2 = 26 ms twdmax = t1min + t2min = 16.5 ms + 17.3 ms = 33.8 ms twdmin = t1max = 24.8 ms twd = 29.3 ms 4.5 ms (15%) A microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly.
Table 6-1.
RWD_OSC k 34 51 91 120
Typical Watchdog Timings
Oscillator Period tosc/s 13.3 19.61 33.54 42.84 Lead Time td/ms 105 154.8 264.80 338.22 Closed Window t1/ms 14.0 20.64 35.32 45.11 Open Window t2/ms 14.7 21.67 37.06 47.34 Trigger Period from Microcontroller Reset Time twd/ms tnres/ms 19.9 29.32 50.14 64.05 4 4 4 4
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7. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage VS Pulse time 500 ms Ta = 25C Output current IVCC 50 mA Pulse time 2 min Ta = 25C Output current IVCC 50 mA WAKE (with 2.7 k serial resistor) KL_15 (with 47 k/100 nF) VBATT (with 47/10 nF) DC voltage Transient voltage due to ISO7637 (coupling 1 nF) INH - DC voltage LIN, VBATT - DC voltage Logic pins (RxD, TxD, EN, NRES, NTRIG, WD_OSC, MODE, TM, DIV_ON, SP_MODE, PV) Output current NRES PVCC DC voltage VCC DC voltage ESD according to IBEE LIN EMC Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (2.7 k, serial resistor) to GND - Pin VBATT (10 nF) to GND HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) MIL-STD-883 (M3015.7) CDM ESD STM 5.3.1 MM ESD EIA/JESD22-A115 ESD STM5.2 AEC-Q100 (002) ESD HBM following STM5.1 with 1.5 k 100 pF - Pin VS, LIN, WAKE to GND Junction temperature Storage temperature Tj Ts INRES -0.3 -0.3 Symbol VS VS Min. -0.3 Typ. Max. +40 +40 Unit V V
VS
27
V
-1 -150
+40 +100
V V
-0.3 -27 -0.3
VS + 0.3 +40 VCC + 0.5V +2 +5.5 +6.5
V V V mA V V
6
KV
3
KV
750
V
200
V
6 -40 -55 +150 +150
KV C C
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8. Thermal Characteristics
Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient, where heat slug is soldered to PCB according to Jedec Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Symbol Rthjc Rthja 150 150 35 165 165 10 170 170 Min. Typ. Max. 10 Unit K/W K/W C C C
9. Electrical Characteristics
5V < VS < 27V, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 1 1.1 Parameters VS Pin Nominal DC voltage range Sleep Mode VLIN > VS - 0.5V VS < 14V Sleep Mode, VLIN = 0V Bus shorted to GND VS < 14V Bus recessive VS < 14V (Tj = 25C) Without load at VCC 1.3 Supply current in Silent Mode Bus recessive VS < 14V (Tj = 125C) Without load at VCC Silent Mode VS < 14V Bus shorted to GND Without load at VCC 1.4 Bus recessive Supply current in Normal VS < 14V Mode Without load at VCC Bus recessive Supply current in Normal VS < 14V Mode VCC load current 50 mA Bus recessive, RXD is low V < 14V Supply current in Fail-safe S Without load at VCC Mode for ATA6628 for ATA6630 VS undervoltage threshold VS undervoltage threshold hysteresis Switch to Unpowered Mode Switch to Fail-safe Mode VS VS VS IVSsleep 5 3 10 27 14 V A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.2
Supply current in Sleep Mode
VS
IVSsleep_short
6
17
30
A
A
VS
IVSsi
20
35
45
A
A
VS
IVSsi
25
40
50
A
A
VS
IVSsi_short
25
50
80
A
A
VS
IVSrec
0.3
0.8
mA
A
1.5
VS
IVSdom
50
53
mA
A
1.6
VS VS VS VS VS
IVSfail IVSfail VSthU VSthF VSth_hys 4 4.3
1.0 1.5 4.2 4.5 0.3
1.5 2.0 4.4 4.9
mA mA V V V
A A A A A
1.7 1.8
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. Electrical Characteristics (Continued)
5V < VS < 27V, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 7 7.1 7.2 7.3 8 8.1 8.2 Parameters RXD Output Pin Low-level output sink current Low-level output voltage Internal resistor to PVCC TXD Input/Output Pin Low-level voltage input High-level voltage input Pull-up resistor VTXD = 0V Fail-safe Mode, wake up VLIN = VS VWAKE = 0V VTXD = 0.4V TXD TXD TXD TXD TXD VTXDL VTXDH RTXD ITXD ITXDwake -0.3 2 125 -3 2 2.5 250 +0.8 VCC + 0.3V 400 +3 8 V V k A mA A A A A A Normal Mode VLIN = 0V VRXD = 0.4V IRXD = 1 mA RXD RXD RXD IRXD VRXDL RRXD 3 5 1.3 2.5 8 0.4 7 mA V k A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
High-level leakage current VTXD = VCC Low-level output sink current EN Input Pin Low-level voltage input High-level voltage input Pull-down resistor Low-level input current Low-level voltage input High-level voltage input Pull-up resistor Mode Input Pin Low-level voltage input High-level voltage input High-level leakage current INH Output Pin High-level voltage Switch-on resistance between VS and INH Leakage current LIN Bus Driver Driver recessive output voltage Driver dominant voltage Load1/Load2 VVS = 7V Rload = 500 Sleep Mode VINH = 0V/27V, VS = 27V IINH = -15 mA VMODE = VCC or VMODE = 0V VNTRIG = 0V VEN = VCC VEN = 0V
EN EN EN EN NTRIG NTRIG NTRIG NTRIG MODE MODE MODE
VENL VENH REN IEN VNTRIGL VNTRIGH RNTRIG INTRIG VMODEL VMODEH IMODE
-0.3 2 50 -3 -0.3 2 125 -3 -0.3 2 -3 250 125
+0.8 VCC + 0.3V 200 +3 +0.8 VCC + 0.3V 400 +3 +0.8 VCC + 0.3V +3
V V k A V V k A V V A
A A A A A A A A A A A
NTRIG Watchdog Input Pin
High-level leakage current VNTRIG = VCC
INH INH INH
VINHH RINH IINHL
VS - 0.75 30 -3
VS 50 +3
V A
A A A
LIN LIN
VBUSrec V_LoSUP
0.9 x VS
VS 1.2
V V
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. Electrical Characteristics (Continued)
5V < VS < 27V, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 8.3 8.4 8.5 8.6 8.7 8.8 Parameters Driver dominant voltage Driver dominant voltage Driver dominant voltage Pull-up resistor to VS Test Conditions VVS = 18V Rload = 500 VVS = 7.0V Rload = 1000 VVS = 18V Rload = 1000 The serial diode is mandatory Pin LIN LIN LIN LIN LIN LIN Input leakage current Driver off VBUS = 0V VBatt = 12V Driver off 8V < VBatt < 18V 8V < VBUS < 18V VBUS VBatt Symbol V_HiSUP V_LoSUP_1k V_HiSUP_1k RLIN VSerDiode IBUS_LIM 0.6 0.8 20 0.4 70 120 30 47 1.0 200 Min. Typ. Max. 2 Unit V V V k V mA Type* A A A A D A
Voltage drop at the serial In pull-up path with Rslave ISerDiode = 10 mA diodes LIN current limitation VBUS = VBatt_max Input leakage current at the receiver including pull-up resistor as specified
8.9
LIN
IBUS_PAS_dom
-1
-0.35
mA
A
Leakage current LIN 8.10 recessive
LIN
IBUS_PAS_rec
10
20
A
A
Leakage current at GND loss, control unit GNDDevice = VS disconnected from ground. VBatt = 12V 8.11 Loss of local ground must 0V < VBUS < 18V not affect communication in the residual network. Leakage current at loss of battery. Node has to sustain the current that VBatt disconnected 8.12 can flow under this VSUP_Device = GND condition. Bus must 0V < VBUS < 18V remain operational under this condition. 8.13 9 9.1 9.2 9.3 9.4 9.5 9.6 Capacitance on pin LIN to GND LIN Bus Receiver Center of receiver threshold Receiver dominant state Receiver recessive state VBUS_CNT = (Vth_dom + Vth_rec)/2 VEN = VCC VEN = VCC
LIN
IBUS_NO_gnd
-10
+0.5
+10
A
A
LIN
IBUS_NO_bat
0.1
2
A
A
LIN
CLIN 0.475 x VS 0.6 x VS 0.028 x VS VS - 2V -27 0.1 x VS 0.5 x VS
20
pF
D
LIN LIN LIN LIN LIN
VBUS_CNT VBUSdom VBUSrec VBUShys VLINH VLINL
0.525 x VS 0.4 x VS 0.175 x VS VS + 0.3V VS - 3.3V
V V V V V V
A A A A A A
Receiver input hysteresis Vhys = Vth_rec - Vth_dom Pre_Wake detection LIN High-level input voltage Pre_Wake detection LIN Low-level input voltage Activates the LIN receiver
LIN
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. Electrical Characteristics (Continued)
5V < VS < 27V, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 10 Parameters Internal Timers VLIN = 0V LIN EN tbus tnorm 30 5 90 15 150 20 s s A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Dominant time for 10.1 wake-up via LIN bus
Time delay for mode 10.2 change from Fail-safe into VEN = VCC Normal Mode via EN pin Time delay for mode change from Normal 10.3 Mode to Sleep Mode via EN pin 10.4 TXD dominant time-out time VEN = 0V
EN
tsleep
2
7
12
s
A
VTXD = 0V
TXD EN LIN
tdom ts_n tmon
27 5 6
55 15 10
70 40 15
ms s ms
A A A
Time delay for mode 10.5 change from Silent Mode VEN = VCC into Normal Mode via EN 10.6 Monitoring time for wake-up over LIN bus
LIN Bus Driver AC Parameter with Different Bus Loads Load 1 (small): 1 nF, 1 k ; Load 2 (large): 10 nF, 500 ; RRXD = 5 k; CRXD = 20 pF; Load 3 (medium): 6.8 nF, 660 characterized on samples; 10.7 and 10.8 specifies the timing parameters for proper operation of 20 Kbit/s, 10.9 and 10.10 at 10.4 Kbit/s THRec(max) = 0.744 x VS THDom(max) = 0.581 x VS VS = 7.0V to 18V tBit = 50 s D1 = tbus_rec(min)/(2 x tBit) THRec(min) = 0.422 x VS THDom(min) = 0.284 x VS VS = 7.6V to 18V tBit = 50 s D2 = tbus_rec(max)/(2 x tBit) THRec(max) = 0.778 x VS THDom(max) = 0.616 x VS VS = 7.0V to 18V tBit = 96 s D3 = tbus_rec(min)/(2 x tBit) THRec(min) = 0.389 x VS THDom(min) = 0.251 x VS VS = 7.6V to 18V tBit = 96 s D4 = tbus_rec(max)/(2 x tBit) VS = 7.0V to 18V
10.7 Duty cycle 1
LIN
D1
0.396
A
10.8 Duty cycle 2
LIN
D2
0.581
A
10.9 Duty cycle 3
LIN
D3
0.417
A
10.10 Duty cycle 4
LIN
D4
0.590
A
10.11 11 11.1
Slope time falling and rising edge at LIN Propagation delay of receiver (Figure 9-1)
LIN
tSLOPE_fall tSLOPE_rise
3.5
22.5
s
A
Receiver Electrical AC Parameters of the LIN Physical Layer, LIN Receiver, RXD Load Conditions (CRXD): 20 pF VS = 7.0V to 18V trx_pd = max(trx_pdr , trx_pdf) VS = 7.0V to 18V trx_sym = trx_pdr - trx_pdf RXD RXD trx_pd trx_sym -2 6 +2 s s A A
Symmetry of receiver 11.2 propagation delay rising edge minus falling edge
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. Electrical Characteristics (Continued)
5V < VS < 27V, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 12 Parameters Test Conditions VS 5.5V INRES = 1 mA 10 k to 5V VCC = 0V VS 5.5V CNRES = 20 pF VS 5.5V CNRES = 20 pF Pin Symbol Min. Typ. Max. Unit Type* NRES Open Drain Output Pin NRES NRES NRES NRES NRES VNRESL VNRESLL treset tres_f 2 1.5 -3 4 0.14 0.14 6 10 +3 V V ms s A A A A A A
12.1 Low-level output voltage 12.2 Low-level output low 12.3 Undervoltage reset time 12.4 Reset debounce time for falling edge Watchdog Oscillator
12.5 Switch off leakage current VNRES = 5.5V 13 13.1 Voltage at WD_OSC in IWD_OSC = -200 A Normal or Fail-safe Mode VVS 4V ROSC = 34 k ROSC = 51 k ROSC = 91 k ROSC = 120 k
WD_OSC WD_OSC
VWD_OSC ROSC tOSC tOSC tOSC tOSC
1.13 34 10.65 15.68 26.83 34.2
1.23
1.33 120
V k s s s s
A A A A A A
13.2 Possible values of resistor Resistor 1% 13.3 Oscillator period 13.4 Oscillator period 13.5 Oscillator period 13.6 Oscillator period 14 Watchdog lead time after 14.1 Reset 14.2 Watchdog closed window 14.3 Watchdog open window 14.4 15 15.1 15.2 Watchdog reset time NRES KL_15 Pin High-level input voltage RV = 47 k Low-level input voltage RV = 47 k VS < 27V VKL_15 = 27V Without external capacitor RV = 47 k , C = 100 nF Positive edge initializes a wake-up
13.3 19.6 33.5 42.8
15.97 23.52 40.24 51.4
Watchdog Timing Relative to tOSC td t1 t2 NRES tnres 3.2 7895 1053 1105 4 4.8 cycles cycles cycles ms A A A A
KL_15 KL_15 KL_15 KL_15 KL_15 WAKE
VKL_15H VKL_15L IKL_15 TdbKL_15 TwKL_15 VWAKEH VWAKEL IWAKE IWAKEL IWAKEL
4 -1 50 80 0.4 VS - 1V -1 -30 -5 30 70 -10 160 2
VS + 0.3V +2 60 250 4.5 VS + 0.3V VS - 3.3V +5 150
V V A s ms V V A A s
A A A A C A A A A A
15.3 KL_15 pull-down current 15.4 Internal debounce time 15.5 KL_15 wake-up time 16 WAKE Pin 16.1 High-level input voltage 16.2 Low-level input voltage 16.3 WAKE pull-up current Time of low pulse for wake-up via WAKE pin
Initializes a wake-up signal VS < 27V, VWAKE = 0V
WAKE WAKE WAKE WAKE
16.4 High-level leakage current VS = 27V, VWAKE = 27V 16.5 VWAKE = 0V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. Electrical Characteristics (Continued)
5V < VS < 27V, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 17 Parameters Test Conditions 4V < VS < 18V (0 mA to 50 mA) Pin Symbol Min. Typ. Max. Unit Type* VCC Voltage Regulator ATA6628 in Normal/Fail-safe and Silent Mode, VCC and PVCC Short-circuited VCC VCC VS, VCC VS, VCC VCC VCC VCC VCC VCC VCC VCC VCC IVCClim Cload VthunN Vhysthun TVCC VCCnor VCClow VD VD VCCline VCCload 50 -240 1.8 2.8 150 320 500 -160 10 3.2 -85 500 0.1 0.1 3.234 VS - VD 3.366 3.366 200 700 0.2 0.5 V V mV mV % % dB mA F V mV s A A A A A A D A D A A A
17.1 Output voltage VCC 17.2
Output voltage VCC at low 3V < VS < 4V VS VS > 3V, IVCC = -15 mA VS > 3V, IVCC = -50 mA 4V < VS < 18V 5 mA < IVCC < 50 mA 10 Hz to 100 kHz CVCC = 10 F VS = 14V, IVCC = -15 mA VS > 4V 0.2 < ESR < 5 at 100 kHz Referred to VCC VS > 4V Referred to VCC VS > 4V
17.3 Regulator drop voltage 17.4 Regulator drop voltage 17.5 Line regulation 17.6 Load regulation 17.7 Power supply ripple rejection
17.8 Output current limitation 17.9 Load capacity 17.10 17.11 17.12 18 VCC undervoltage threshold Hysteresis of undervoltage threshold
Ramp-up time VS > 4V to CVCC = 2.2 F VCC = 3.3V Iload = -5 mA at VCC 5.5V < VS < 18V (0 mA to 50 mA)
VCC Voltage Regulator ATA6630 in Normal/Fail-safe and Silent Mode, VCC and PVCC Short-circuited VCC VCC VS, VCC VS, VCC VS, VCC VCC VCC VCC VCC VCC VCC VCC VCC IVCClim VthunN VthunN Vhysthun tVCC VCCnor VCClow VD1 VD2 VD3 VCCline VCCload 50 -240 1.8 4.2 250 370 600 -130 10 4.8 -85 0.1 0.1 400 4.9 VS - VD 5.1 5.1 250 600 200 0.2 0.5 V V mV mV mV % % dB mA F V mV s A A A A A A A D A D A A A
18.1 Output voltage VCC 18.2
Output voltage VCC at low 4V < VS < 5.5V VS VS > 4V, IVCC = -20 mA VS > 4V, IVCC = -50 mA VS > 3.3V, IVCC = -15 mA 5.5V < VS < 18V 5 mA < IVCC < 50 mA 100 kHz 10 Hz to 100 kHz CVCC = 10 F VS = 14V, IVCC = -15 mA VS > 5.5V 0.2 < ESR < 5 at 100 kHz Referred to VCC VS > 5.5V Referred to VCC VS > 5.5V CVCC = 2.2 F Iload = -5 mA at VCC
18.3 Regulator drop voltage 18.4 Regulator drop voltage 18.5 Regulator drop voltage 18.6 Line regulation 18.7 Load regulation 18.8 Power supply ripple rejection
18.9 Output current limitation 18.10 Load capacity 18.11 18.12 18.13 VCC undervoltage threshold Hysteresis of undervoltage threshold Ramp-up time VS > 5.5V to VCC = 5V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. Electrical Characteristics (Continued)
5V < VS < 27V, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 19 Parameters DIV_ON Input Pin DIV_ON DIV_ON VDIV_ON = VCC VDIV_ON = 0V DIV_ON DIV_ON VDIV_ON VDIV_ON RDIV_ON IDIV_ON -0.3 2 125 -3 -0.3 2 50 -3 125 250 +0.8 VCC + 0.3 400 +3 +0.8 VCC + 0.3 200 +3 V V k A V V k A A A A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
19.1 Low-level voltage input 19.2 High-level voltage input 19.3 Pull-down resistor 19.4 Low-level input current 20 SP_MODE Input Pin 20.1 Low-level voltage input 20.2 High-level voltage input 20.3 Pull-down resistor 20.4 Low-level input current 21 VSP_MODE = VCC VSP_MODE = 0V VS = 7V to 18V RLIN = 500 , CLIN = 600 pF VS = 7V to 18V VS = 14V RLIN = 500 , CLIN = 600 pF
SP_MODE VSP_MODE SP_MODE VSP_MODE SP_MODE RSP_MODE SP_MODE ISP_MODE
LIN Driver in High-speed Mode(VSP_Mode = VCC) LIN LIN LIN SP tSL_fall tSL_rise 115 1 2 2 3 kBaud s s C A A
21.1 Transmission Baud rate 21.2 Slope time LIN falling edge
Slope time LIN rising 21.3 edge, depending on RC-load 22 ATA6628 Voltage Divider 22.1 Divider ratio 22.2 Divider ratio error 22.3 Divider temperature drift 22.4 VBATT range of divider linearity
VS = 5V to 18V
PV -2
1:6 +2 3 % ppm/C 18 220 3.1 2 1:6 -2 3 +2 % ppm/C 27 220 4.8 2 5.2 V A V pF 3.5 V A V pF
A A C A A A
VBATT VBATT = 14V VBATT 18V to 40V VBATT VBATT PV VS = 5V to 27V PV
5 100 3
22.5 VBatt input current Maximum output Voltage 22.6 at PV 22.7 Pin capacitance 23 ATA6630 Voltage Divider 23.1 Divider ratio 23.2 Divider ratio error 23.3 Divider temperature drift VBATT range of divider 23.4 linearity 23.5 VBatt input current 23.6 Maximum output Voltage at PV
A A C A A A
VBATT VBATT = 14V VBATT 27V to 40V VBATT PV PV
5 100 4.4
23.7 Pin capacitance
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
29
9117E-AUTO-07/10
Figure 9-1.
Definition of Bus Timing Characteristics
tBit tBit tBit
TXD (Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min)
Thresholds of receiving node1
Thresholds of receiving node2
tBus_dom(min)
tBus_rec(max)
RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1)
RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2)
30
ATA6628/ATA6630 [Preliminary]
9117E-AUTO-07/10
ATA6628/ATA6630 [Preliminary]
Figure 9-2. Typical Application Circuit
Ignition KL15 debug
VBattery KL30
10 F + 47 10 nF
100 nF
47 k 100 nF
Master node pull-up
VCC
+
MODE
KL_15
PVCC
10 k 1 k
100 nF 10 F
10 k
VS
20
19
18
17
16 15
VCC EN NTRIG
10 k
VBATT EN NTRIG 2.7 k WAKE GND
1 2 3 4 5 6 7 8 9 10
TM WD_OSC NRES TXD 51 k
ATA6628 ATA6630
MLP 5 mm 5 mm 0.65 mm pitch 20 lead
14 13 12 11
Wake switch
DIV_ON
RXD TXD RESET ADC DIV_ON SP_MODE GND INH
MODE
RXD
LIN
PV
Microcontroller
SP_
220 pF
LIN sub bus
INH
31
9117E-AUTO-07/10
Figure 9-3.
Application Circuit with External NPN-Transistor
Ignition KL15 10 F + 47 22 nF
+
VBattery KL30 100 nF T1 *) MJD31C 2.2 F 100 nF 10 F VCC
+
Debug 47 k Master node pull-up 100 nF MODE
KL_15
PVCC
3.3 10 k VS
10 k
1 k
10 k VBATT VCC EN NTRIG 2.7 k EN NTRIG WAKE GND Wake switch
1 2 3 4 5
20
19
18
17
16 15
TM WD_OSC NRES TXD 51 k
ATA6628/ ATA6630
QFN 5x5 mm 0.65 mm pitch 20 lead
14 13 12 11
6
7
8
9
10
PV
RXD TXD RESET ADC DIV_ON SP_MODE GND INH
SP_MODE
LIN
RXD
DIV_ON
Microcontroller
220 pF
*) Note that the output voltage PVCC is no longer short-ciruit protected when boosting the output current by an external NPN-transistor.
32
ATA6628/ATA6630 [Preliminary]
9117E-AUTO-07/10
LIN Sub Bus
INH
ATA6628/ATA6630 [Preliminary]
Figure 9-4. LIN Slave Application with Minimum External Devices
VBattery KL30 22 F + VCC 100 nF
VCC
VS
100 nF
MODE
10 F + KL_15 PVCC
10 k
20
19
18
17
16 15
VBATT VCC EN VCC EN NTRIG WAKE GND
1 2 3 4 5 6 7 8 9 10 QFN 5x5 mm 0.65 mm pitch 20 lead
TM WD_OSC NRES TXD INH
ATA6628/ ATA6630
14 13 12 11
Microcontroller
SP_MODE
RXD
DIV_ON
LIN
PV
LIN Sub Bus
R3
220 pF RXD TXD RESET GND
Note: No watchdog, no Battery voltage measurement, no local wake up, INH output not used
33
9117E-AUTO-07/10
10. Ordering Information
Extended Type Number ATA6628-PGPW ATA6630-PGPW ATA6628-PGQW ATA6630-PGQW Package QFN20 QFN20 QFN20 QFN20 Remarks 3.3V LIN system-basis-chip, Pb-free, 1.5k, taped and reeled 5V LIN system-basis-chip, Pb-free, 1.5k, taped and reeled 3.3V LIN system-basis-chip, Pb-free, 6k, taped and reeled 5V LIN system-basis-chip, Pb-free, 6k, taped and reeled
11. Package Information
Package: VQFN_5 x 5_20L Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances 0.05 0.05-0.05 Top 20 Pin 1 identification 1 15 16 20 1
0
Bottom 3.10.15
5 0.2 5 0.90.1
11 10 6
5
0.65 nom. 2.6
Drawing-No.: 6.543-5129.01-4 Issue: 2; 09.02.07 0.280.07
0.60.1
technical drawings according to DIN specifications
34
ATA6628/ATA6630 [Preliminary]
9117E-AUTO-07/10
ATA6628/ATA6630 [Preliminary]
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9117E-AUTO-07/10 History * Section 6 "Watchdog" on pages 20 to 21 changed * Features on page 1 changed * Pin Description table: row Pin 16 changed * Text under heading 3.3, 3.8, 3.11, 3.12, 4.2, 5.1, 5.5, 6 changed * Figures 4-5, 6-1 changed * Figure 9-1 heading changed * Figures 9-2 and 9-3 added * Abs.Max.Rat.Table -> Parameter text in row "ESD according..." changed * Abs.Max.Rat.Table -> Values in row "ESD HBM following...." changed * El.Char.Table -> rows changed: 1.2, 1.3, 1.6, 1.7, 7.1,10.4, 17.12, 12.1, 12.2, 17.5, 17.6, 17.7, 17.8, 18.6, 18.7, 18.8, 18.9, 18.13, 11.5, 23.5 * El.Char.Table -> row 8.13 added * Complete datasheet: "LIN 2.1 specicfication" changed in "LIN 2.0, 2.1 specicfication or "2.x" * Features on page 1 changed * Description text on page 1 changed * Pin Descritption table rows changed: 8, 11, 12 * Sections changed: 3.9, 3.10, 3.15, 3.20, 3.21, 4.1, 4.2, 4.3, 4-7, 5.1, 5.5, 5.6 * New section 4.4 added (the following section numbers automatically changes...) * Table Abs. Max. Ratings: changes in following rows: WAKE, INH - DC voltage, ESD HBM following STM5.1 * Table El. Characteristics: changes in folloring rows: 1.2, 1.3, 7.2, 8.7, 8.11, 8.12, 13.1, 15.5, 17.9, 18.10, 21 to 23.7 new rows 10.6, 12.5, 18.8 added (the following counting changed) row 20.5 deleted * Figure heading changed: 4-7 * Figures changed: 1-1, 4-3, 4-4, 4-5, 4-6, 4-7, 9-2 * Table headings changed: 3-1
9117D-AUTO-05/10
9117C-AUTO-10/09
35
9117E-AUTO-07/10
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9117E-AUTO-07/10

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